🧠 Silicon Networking RTL Design Senior Engineer – Google Cloud
Job Description
Location: Bengaluru, Karnataka, India | Company: Google
✅ Summary
Google Cloud is hiring a Senior RTL Design Engineer with expertise in silicon networking, ASIC development, and custom chip design to build the next generation of AI/ML hardware and data center accelerators. Based in Bengaluru, India, this role is central to shaping TPU (Tensor Processing Unit) architecture that powers mission-critical AI and networking workloads across the globe.
If you’re experienced in Verilog/SystemVerilog, micro-architecture for networking subsystems, and SoC integration, and are looking to work on some of the most advanced silicon technologies in the world — this opportunity is for you.
📋 Job Details at a Glance
| Job Title | Silicon Networking RTL Design Senior Engineer |
|---|---|
| Location | Bengaluru, Karnataka, India |
| Job Type | Full-Time |
| Experience Required | 8+ Years in ASIC Development |
| Tools & Languages | Verilog, SystemVerilog, VHDL, Python, Perl |
| Key Areas | Networking IPs, SoC, RTL Design, DFT |
| Industry Focus | AI/ML, Cloud Infrastructure, Custom Silicon |
| Shift | Day Shift / Hybrid Model |
| Team | ML, Systems & Cloud AI (MSCA) |
💼 Role Overview
As a Senior RTL Design Engineer – Silicon Networking at Google Cloud, you’ll be part of the team developing ASICs that optimize traffic flow in hyperscale data centers and accelerate AI/ML workloads via custom hardware. Your role will involve designing, implementing, and verifying complex digital IPs and networking subsystems, collaborating closely with architecture, firmware, verification, and physical design teams.
This is a hands-on leadership position at the intersection of AI hardware acceleration, chip performance optimization, and next-gen networking technologies.
🔧 Key Responsibilities
- Lead microarchitecture design and implementation of high-performance IP blocks in the networking domain.
- Collaborate with cross-functional teams (Architecture, Firmware, Software) to translate features into detailed micro-architecture specifications.
- Contribute to ASIC design methodology, including synthesis, power analysis, DFT, and verification.
- Work closely with Design Verification and Physical Design teams to ensure robust RTL designs.
- Optimize for power, performance, and area (PPA) using advanced design techniques.
- Deliver production-quality RTL for next-gen data center silicon accelerators.
🧠 Required Skills & Qualifications
Minimum Qualifications
- Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field (or equivalent experience).
- 8+ years of experience in ASIC development, especially with Verilog/SystemVerilog or VHDL.
- Solid experience with ASIC verification, synthesis, timing, DFT, and power analysis.
- Expertise in networking subsystems: packet processing, bandwidth management, congestion control, etc.
Preferred Qualifications
- Master’s degree in a technical field.
- Proficiency in scripting languages like Python or Perl.
- Experience with SoC integration flows and complex chip-level designs.
- Strong knowledge of high-performance, low-power design techniques.
- Familiarity with bus architectures, NoC (Network on Chip), and memory hierarchy.
🌍 About Google Cloud & MSCA
The ML, Systems & Cloud AI (MSCA) team at Google designs the hardware and infrastructure powering services like Search, YouTube, and Vertex AI. This role contributes directly to the future of TPU silicon, supporting the workloads of billions of users globally.
At Google, you’ll join an inclusive and innovative engineering culture where ideas move quickly and have real impact. Collaborate with the best minds in AI hardware, cloud computing, and chip design.
🚀 Apply Now
Ready to design the silicon behind Google’s AI/ML future?
👉 Apply Now on the Official Google Careers Page
Choose “Bengaluru, India” as your preferred working location when applying.