Silicon Networking RTL Design Senior Engineer – Google Cloud
Job Description
Summary
Looking for an exciting opportunity as a Silicon Networking RTL Design Senior Engineer? Join Google Cloud’s innovative hardware team in Bengaluru, Karnataka, India, and be at the forefront of designing next-generation ASICs and silicon solutions powering Google’s AI/ML workloads. This role focuses on ASIC design, RTL development, microarchitecture, and verification in networking domains such as packet processing, congestion control, and bandwidth management. If you have a strong background in Verilog/SystemVerilog, VHDL, ASIC verification, and microarchitecture design, this is your chance to contribute to cutting-edge TPU technology and hyperscale cloud infrastructure.
Job Details at a Glance
| Job Title | Silicon Networking RTL Design Senior Engineer |
|---|---|
| Location | Bengaluru, Karnataka, India |
| Job Type | Full-time |
| Experience Required | 8+ years in ASIC design, RTL, and networking domain |
| Key Skills | Verilog, SystemVerilog, VHDL, ASIC verification, microarchitecture |
| Technologies | ASIC design tools, scripting (Python/Perl preferred), Google TPU |
Responsibilities
- Design and own the microarchitecture and RTL implementation of complex IPs and subsystems in the networking domain, including packet processing and congestion control.
- Collaborate closely with Architecture, Firmware, Software, and Physical Design teams to finalize features and develop detailed microarchitecture specifications.
- Lead design methodology, code reviews, debug processes, and coordinate with design verification teams for high-quality silicon delivery.
- Identify and implement improvements focused on power, performance, and area (PPA) optimization.
- Drive innovation and apply best practices in ASIC design and verification to support Google’s TPU and AI/ML systems.
Skills & Qualifications
Minimum Qualifications
- Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field (or equivalent practical experience).
- 8+ years experience in ASIC development using Verilog/SystemVerilog and VHDL.
- Hands-on experience with ASIC design verification, synthesis, timing and power analysis, and Design for Testing (DFT).
- Expertise in microarchitecture and IP/subsystem design in networking domains such as bandwidth management, congestion control, and packet processing.
Preferred Qualifications
- Experience with scripting languages like Python or Perl to automate and optimize workflows.
- Knowledge of SoC design and integration flows.
- Familiarity with high-performance and low-power design techniques.
- Understanding of bus architectures, Network-on-Chip (NoC), processor design, accelerators, or memory hierarchies.
Why Join Google Cloud?
Google Cloud is a leader in cloud infrastructure, powering billions of users worldwide with secure, scalable, and reliable technology. As part of our hardware team, you will work on next-generation TPU accelerators that fuel AI/ML innovation globally. Join a collaborative, dynamic environment where your expertise helps shape the future of hyperscale computing and cloud hardware.
Apply Now
Ready to engineer the future of cloud hardware? Apply for the Silicon Networking RTL Design Senior Engineer position at Google Cloud today.